1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors and used for generating strain in channel regions of the transistors.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed in and on a semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above, if a planar transistor architecture is considered, or generally adjacent to, if any other transistor architecture, such as a fin-type transistor or the like, is considered, the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel adjacent to the gate dielectric layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the transistors. For this reason and in view of generally increasing packing density of integrated circuits, the reduction of the channel length may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 3 GigaPascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for controlling the desired intrinsic stress.
In current CMOS logic technology, the dielectric layer stack formed above the basic transistors, therefore, typically consists of the contact etch stop layer having a thickness of several hundred Angstrom, which is frequently directly deposited on the exposed surface areas of the transistors, for instance after the silicidation process, which is frequently applied so as to enhance overall conductivity of drain and source areas and possibly of the gate electrode structure, depending on the process strategy used. Thereafter, an interlayer dielectric material, also referred to as pre-metal deposition layer, with a thickness of several thousand Angstrom is formed, frequently as a silicon oxide material, which may subsequently be patterned so as to receive respective contact openings which are then filled with an appropriate contact material, such as tungsten and the like. Upon applying the above-described technique, the etch stop layer is formed so as to induce tensile and/or compressive strain in the channel regions of the respective transistors in order to enhance transistor characteristics, i.e., drive current capability and the like. In this strain-inducing mechanism, performance improvement of the various transistors depends on the internal stress level of the etch stop layer and the thickness of this layer. Since generally the thickness of the etch stop layer is substantially determined by overall design rules, which demand a certain minimal pitch between neighboring gate electrode structures, there is an ongoing tendency to improve transistor characteristics by appropriately increasing the internal stress level of the etch stop layer. It appears, however, that simply increasing the internal stress level may not necessarily result in an increased strain level in the respective channel regions since the stress transfer mechanism strongly depends on the adhesion characteristics of the highly stressed dielectric material when formed on exposed surface areas of the transistors, as will be explained with reference to FIG. 1.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, or any other appropriate carrier material for forming thereon a semiconductor layer 102 in and above which transistors 150a, 150b are formed. Typically, the semiconductor layer 102 may represent a crystalline semiconductor material which may comprise a significant amount of silicon since silicon is presently a preferred base material for fabricating sophisticated CMOS devices in compliance with volume production techniques. As usual, the semiconductor layer 102 is typically laterally delineated in a plurality of active regions 102a wherein, for convenience, a single active region is shown in FIG. 1. Furthermore, any isolation structures for laterally delineating the active region 102a are not shown. In the example shown, the two transistors 150a, 150b are formed in and above the active region 102a, wherein it should be appreciated that a single transistor or more than two transistors may be formed in the active region 102a, depending on the overall requirements. For example, in densely packed device areas, such as memory areas and the like, a plurality of individual transistors may be formed in and above a single active region. The transistors 150a, 150b are illustrated as transistors having a planar transistor architecture in which drain and source regions 152 laterally delineate a channel region 151, which may be understood as a region with a substantially two-dimensional interface area with respect to a gate dielectric material 161 of gate electrode structures 160a, 160b, respectively, as is also discussed above. It should be appreciated that, in other transistor architectures, the channel region 151 may have corresponding interface areas that may represent different planes and may thus provide a three-dimensional transistor architecture, for instance as is known for fin-type transistors, also referred to as FinFET. Furthermore, the gate electrode structures 160a, 160b may comprise one or more electrode materials 162, 163 depending on the overall configuration. In this respect, it should be appreciated that the gate electrode structures 160a, 160b may represent complex structures including high-k dielectric materials in combination with appropriately selected electrode materials in order to increase the overall productivity of the electrode materials and also adjust an appropriate work function of the gate electrode structures 160a, 160b. In the example shown, the gate electrode structures 160a, 160b may comprise a semiconductor material, possibly in combination with appropriate metal-containing materials within the electrode material 162 and a metal silicide in the material 163, wherein, however, any other configuration may be used.
Moreover, typically, metal silicide regions 153 are formed within the drain and source regions 152 in order to reduce contact resistance and improve the series resistance of the transistors 150a, 150b. Furthermore, an etch stop layer 120 of high internal stress level is formed above the transistors 150a, 150b so as to induce a desired type of strain 151s in the channel regions 151. Since typically P-channel transistors suffer from a reduced charge carrier mobility compared to N-channel transistors, it is of great importance to appropriately increase, in particular, the compressive strain in the channel regions of P-channel transistors. Hence, in the example shown, the transistors 150a, 150b represent P-channel transistors in which the etch stop layer 120 is provided with high internal compressive stress so as to efficiently improve drive current capability and switching speed of the transistors 150a, 150b. Furthermore, as discussed above, a pre-metal deposition layer or an interlayer dielectric material 124 in the form of silicon dioxide and the like is typically formed above the etch stop layer 120.
The transistors 150a, 150b may be formed on the basis of any appropriate manufacturing strategy, for instance, forming the gate electrode structures 160a, 160b in accordance with the required design rules which, in sophisticated applications, may require a gate length of 40 nm and less, thereby necessitating the application of highly sophisticated patterning strategies. As discussed above, if required, sophisticated high-k metal gate electrode structures may be implemented. Thereafter, the drain and source regions 152 are typically formed by implantation, epitaxial growth techniques and the like, wherein typically a spacer structure 164 of the gate electrode structures 160a, 160b is used for appropriately defining the lateral profile of the drain and source regions 152. It should be appreciated that other strain-inducing mechanisms may be implemented, for instance, by incorporating a strain-inducing semiconductor material by applying stress memorization techniques and the like so as to further improve the overall transistor characteristics. After any high temperature processes, for instance for activating implanted dopants and the like, the metal silicide 153 is formed on the basis of well-established silicidation techniques, thereby completing the basic transistor configurations.
Thereafter, the etch stop layer 120 is formed so as to have a desired high internal stress level in order to induce the strain 151s. To this end, silicon nitride has proven to be a viable candidate for being deposited on the basis of well-established plasma enhanced chemical vapor deposition (CVD) techniques with high internal compressive stress if P-channel transistors are considered, while also providing the required etch stop capabilities. Consequently, a plurality of deposition recipes have been developed in order to control process parameters, such as gas flow rates, ion bombardment, pressure and the like, in order to deposit the silicon nitride material with high intrinsic compressive stress. Although internal stress levels of 3 GPa and even higher may be achieved, it turns out that the high internal stress level in the etch stop layer may not be transferred as efficiently into the channel region 151 as one would expect. One reason is seen in the adhesion characteristics of the silicon nitride material with respect to the exposed surface areas of the transistors 150a, 150b. For this reason, it has been proposed to provide the etch stop layer 120 in the form of a bi-layer including an adhesion layer 121, which has a significantly lower internal stress level and which is designed to provide superior adhesion to the transistor surface areas, while a subsequent layer 122 may provide the required high internal stress level. Consequently, typically two different deposition recipes are applied in forming the bi-layer 120 so as to obtain superior adhesion for the layer 121 and to obtain a very high internal stress level for the layer 122. In some cases, as indicated by the component 123, an additional etch stop layer, for instance in the form of a thin silicon dioxide material, may be provided, for instance if the layer 120 is to be patterned so as to provide etch stop layers of different stress characteristics above different transistor types. In other cases, the bi-layer 120 is directly formed on exposed surface areas of the transistors 150a, 150b. 
Basically, the bi-layer 120 provides a very efficient strain-inducing mechanism wherein, in sophisticated applications, the adhesion layer may be provided with a thickness of approximately 10 nm with a stress level of 1.7-1.9 GPa, while the layer 122 may have a desired increased thickness with an internal stress level of 3 GPa and significantly higher, for instance up to 3.6 GPa. Since generally the mechanical force induced by the internal stress level of the layer 120 is simply determined by the internal stress level times the thickness of the layer 120, the average stress level is determined by the overall thickness and the combined stress levels of the layers 121 and 122. Hence, in order to increase the finally obtained strain 151s in the channel region 151, an increase in overall thickness and in the average stress level would be highly desirable which, however, is not compatible with the demand for ever increasing packing density in sophisticated semiconductor devices. That is, due to a reduced pitch of neighboring gate electrode structures, such as the structures 160a, 160b, the overall thickness of the bi-layer 120 has to be adapted so as to allow a reliable deposition of the stressed silicon nitride material in the spaces between these neighboring structures, thereby requiring a deposition thickness of approximately 40 nm for semiconductor devices including gate electrode structures having a gate length of approximately 40 nm and less.
This deposition recipe represents a sophisticated deposition technique for forming the bi-layer 120 so as to obtain a high desired compressive strain in the channel regions 151. The deposition may be performed in a process environment established on the basis of a deposition tool that is available from Applied Materials Inc. under the name Producer, which is appropriately configured to process semiconductor substrates of 300 mm in diameter. In a first step, the adhesion layer 121 is formed by first setting up the process chamber of the deposition tool, wherein the substrate 101 is positioned on an appropriate substrate holder that enables the adjustment of the temperature of the substrate to a desired value, which may be in the range of 300-550° C., for instance 480° C., while a spacing of the substrate 101 with respect to a shower head of the process chamber is adjusted to be in a range from 250-350 mil. Furthermore, a desired pressure is established by applying precursor gases in the form of silane and ammonia in combination with carrier gases in the form of nitrogen and argon.
Furthermore, in the next step of forming the adhesion layer 121, the actual deposition of the silicon nitride material is initiated by supplying low frequency power to the process atmosphere within the process chamber, thereby creating a plasma which in turn generates respective radicals that interact with exposed surface areas, as is well known in the art. During the deposition step, low frequency power of approximately 30-150 W may be applied, thereby obtaining a thickness of approximately 10 nm for a deposition time of 15 seconds.
Thereafter, two transition steps are performed so as to reconfigure the deposition atmosphere within the process chamber in order to enable the deposition of the top layer 122 with the desired high internal stress level. In the first step of the two transition steps, high frequency power is supplied to the process atmosphere, while, in the second transition step, additionally the argon flow rate may be increased in order to obtain increased ion bombardment during the deposition process. Thus, during the transition steps, a plasma atmosphere is maintained in order to prepare the conditions for the subsequent deposition of the layer 122. In the next step, the previously adjusted process conditions are maintained for a time of 72-110 seconds, thereby obtaining a thickness of approximately 30 nm for the layer 122. Thereafter, the deposition process is terminated by applying purge and pump steps.
In Table 1 below there are listed respective parameter values that may be used in the above-described process sequence for forming the bi-layer 120.
TABLE 1Formation of adhesion-layer 121Set-up 15 sec:T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils,SiH4 = 40-120 sccm, NH3 = 50-200 sccm,N2 = 1000-3000 sccm, Ar = 1500-3000 sccm,Deposition 15 sec (100 Å):T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils, LF power = 30-150 Watts,SiH4 = 40-120 sccm, NH3 = 50-200 sccm,N2 = 1000-3000 sccm, Ar = 1500-3000 sccm,Transition stepsTransition step1:Pre1 1 sec, T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils, LF power = 20-120 W, HF power = 60-160 W,SiH4 = 40-120 sccm, NH3 = 50-200 sccm,N2 = 1000-3000 sccm, Ar = 1500-3000 sccm,Transition step4:Pre2 1 sec, T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils, LF power = 20-120 W, HF power = 60-160 W,SiH4 = 40-120 sccm, NH3 = 50-200 sccm,N2 = 1000-2000 sccm, Ar = 2000-5000 sccm,Formation of high stress top layer 122Deposition 70-110 sec (300 Å):T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils, LF power = 20-130 W, HF power = 60-160 W,SiH4 = 40-120 sccm, NH3 = 50-200 sccm,Ar = 2000-5000 sccm, H2 = 2000-5000 sccm,Purge & PumpPurge 10 sec:T = 480° C. (300-550° C.), p = 1.5-2.5 Torr,Spacing = 250-350 mils, LF power = 0 W, HF power = 0 W,SiH4 = 0 sccm, NH3 = 0 sccm, Ar = 2000-5000 sccm, H2 = 0 sccm,Pump 10 sec:T = 480° C. (300-550° C.), TV open,Spacing = Lift position, LF power = 0 W, HF power = 0 W,SiH4 = −1, NH3 = −1, Ar = −1, H2 = −1,
By using the above-specified deposition recipe, the internal stress levels as indicated above may be obtained. However, the resulting strain level in the channel regions is less than expected and a further improvement of the characteristics of P-channel transistors is highly desirable. It turns out, however, that simply reducing the thickness of the adhesion layer 121 and increasing the thickness of the top layer 122 by the same amount has actually not resulted in higher forces and improved performance of the P-channel transistors since a loss of adhesion may be accompanied by reducing the thickness of the adhesion layer 121.
In view of the situation described above, the present disclosure relates to process techniques and semiconductor devices in which an efficient strain-inducing mechanism may be provided on the basis of a highly stressed dielectric material, while avoiding or at least reducing the effects of one or more of the problems identified above.